Ecosyste.ms: Repos
An open API service providing repository metadata for many open source software ecosystems.
GitHub topics: verilog-a
ACMmodel/MOSFET_model
A simple MOSFET model with only 5-DC-parameters for circuit simulation
Size: 7.76 MB - Last synced: 10 days ago - Pushed: 10 days ago - Stars: 29 - Forks: 5
thennen/Synaptogen
A fast generative model for stochastic memory cells
Language: Julia - Size: 57.6 KB - Last synced: 16 days ago - Pushed: 16 days ago - Stars: 2 - Forks: 0
rpm2003rpm/vagen
Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)
Language: Python - Size: 1.58 MB - Last synced: 13 days ago - Pushed: about 1 month ago - Stars: 1 - Forks: 0
pascalkuthe/OpenVAF
An innovative Verilog-A compiler
Language: Rust - Size: 10.5 MB - Last synced: 2 months ago - Pushed: 7 months ago - Stars: 96 - Forks: 11
NVerilog/NVerilogParser
A Verilog-AMS parser for .NET
Language: C# - Size: 668 KB - Last synced: 3 months ago - Pushed: over 1 year ago - Stars: 2 - Forks: 4
nikacvet/vscode-verilogA
Language support in Visual Studio Code for VerilogA
Language: TypeScript - Size: 1020 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0
pyadms/pyadms
Python Automatic Device Model Synthesizer
Language: C++ - Size: 10.4 MB - Last synced: 27 days ago - Pushed: 3 months ago - Stars: 1 - Forks: 0
rpm2003rpm/stg2veriloga
converts a stg (.g file generated by workcraft) to a verilogA model
Language: Python - Size: 165 KB - Last synced: 5 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0
gnucap/gnucap-adms
defunct. use repo on savannah
Size: 1.39 MB - Last synced: 7 months ago - Pushed: over 5 years ago - Stars: 5 - Forks: 2
posvirus/RTE-Sim
Compact model for light propagation simulation in fNIRS systems
Size: 760 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 0 - Forks: 0
akashlevy/pyxbar
Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations
Language: SourcePawn - Size: 184 MB - Last synced: 10 months ago - Pushed: over 4 years ago - Stars: 10 - Forks: 3
akashlevy/WP-RRAM-SPICE-Model
A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley
Size: 1.95 KB - Last synced: 10 months ago - Pushed: over 3 years ago - Stars: 4 - Forks: 2
pouryahoseini/Genetic-Algorithm-Processor
A digital genetic algorithm processor
Language: Verilog - Size: 3.99 MB - Last synced: about 1 year ago - Pushed: about 4 years ago - Stars: 2 - Forks: 1
