SpiceSharp/SpiceSharpParser

SPICE netlists parser for .NET

Language: C# - Size: 8.42 MB - Last synced: 2 days ago - Pushed: 20 days ago - Stars: 25 - Forks: 6

nturley/netlistsvg

draws an SVG schematic from a JSON netlist

Language: JavaScript - Size: 1.02 MB - Last synced: 19 days ago - Pushed: 4 months ago - Stars: 587 - Forks: 72

byuccl/spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Language: Python - Size: 46 MB - Last synced: 24 days ago - Pushed: 3 months ago - Stars: 85 - Forks: 19

emsec/hal

HAL – The Hardware Analyzer

Language: C++ - Size: 2.4 GB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 510 - Forks: 73

google/pcbdl 📦

PCB Design Language: A programming way to design schematics.

Language: Python - Size: 6.12 MB - Last synced: 23 days ago - Pushed: about 3 years ago - Stars: 149 - Forks: 25

circuitgraph/circuitgraph

Tools for working with circuits as graphs in python

Language: Verilog - Size: 10.5 MB - Last synced: 25 days ago - Pushed: 7 months ago - Stars: 95 - Forks: 14

ganeshgore/spydrnet-physical

This is a SpyDrNet Plugin for a physical design related transformations

Language: Python - Size: 16.7 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 10 - Forks: 4

najaeda/naja

Structural Netlist API (and more) for EDA post synthesis flow development

Language: Python - Size: 7.55 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 40 - Forks: 9

pablov55/Beginner-s-Guide-to-KiCad

This guide will teach you all the basics of KiCad from schematic building to PCB design. It will also teach you how to add libraries, create your own symbols & footprints, export the drill and gerber files, and many more tips to get you started on your KiCad journey!

Language: HTML - Size: 5.29 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 1 - Forks: 0

najaeda/naja-verilog

A standalone structural (gate-level) verilog parser

Language: C++ - Size: 193 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 20 - Forks: 1

byuccl/spydrnet-tmr

TMR utilities for the SpyDrNet project

Language: Python - Size: 10.7 MB - Last synced: 24 days ago - Pushed: 7 months ago - Stars: 4 - Forks: 2

electron-lang/electron

A mixed signal netlist language (pre-alpha)

Language: TypeScript - Size: 2.71 MB - Last synced: 23 days ago - Pushed: almost 6 years ago - Stars: 58 - Forks: 6

muhammadtalhasami/openlane

This is my openlane repository in which we perform synthesis of our design/module.

Language: Tcl - Size: 384 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

DevinduDh/LTspice-projects

LTSpice projects

Language: AGS Script - Size: 45.9 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

jamestiotio/compstruct

SUTD 2020 50.002 Computation Structures Code Dump

Language: C - Size: 89.7 MB - Last synced: 29 days ago - Pushed: about 2 years ago - Stars: 3 - Forks: 0

LCSR-lab/MODNET

MODNET (MODify NETlist): VHDL/Verilog Fault Injection system

Language: Python - Size: 112 KB - Last synced: 7 months ago - Pushed: almost 3 years ago - Stars: 1 - Forks: 0

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Language: VHDL - Size: 46.9 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 2 - Forks: 1

jvestman/skimibowi

SKiDL Microcontroller Board Wizard

Language: Python - Size: 522 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 5 - Forks: 0

emsec/hal-benchmarks

Benchmark suite for HAL

Language: VHDL - Size: 9.16 MB - Last synced: 2 months ago - Pushed: over 3 years ago - Stars: 8 - Forks: 1

amfl/short-circuit

tile-based digital logic sandbox

Language: Python - Size: 148 KB - Last synced: 10 months ago - Pushed: over 2 years ago - Stars: 3 - Forks: 1

circuitgraph/circuitsim

Perform gate-level simulations from python

Language: Python - Size: 44.9 KB - Last synced: 25 days ago - Pushed: about 1 year ago - Stars: 3 - Forks: 0

LCSR-lab/NetFi3

NetFI-3: Netlist Fault Injection system - Version 3

Language: TeX - Size: 23.2 MB - Last synced: 10 months ago - Pushed: almost 4 years ago - Stars: 0 - Forks: 0

akashlevy/pyxbar

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

Language: SourcePawn - Size: 184 MB - Last synced: 10 months ago - Pushed: over 4 years ago - Stars: 10 - Forks: 3

jimwang99/parser-for-chip-design

A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).

Language: Python - Size: 145 KB - Last synced: 8 months ago - Pushed: almost 9 years ago - Stars: 24 - Forks: 7

arasgungore/netlist-solver

A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit.

Language: MATLAB - Size: 531 KB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 11 - Forks: 2

aaanthonyyy/CircuitNet

A hand-drawn schematic sketch recognizer and converter. Traditional object detection techniques built using OpenCV; deep learning classification powered by TensorFlow 2 using the Keras API.

Language: Jupyter Notebook - Size: 4.8 MB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 6 - Forks: 1

rohankalbag/logic-simulator

Course Assignment - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay

Language: Jupyter Notebook - Size: 95.7 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

shishir-dey/vhdl-samples

Contains VHDL netlists of basic digital circuits.

Language: VHDL - Size: 1.09 MB - Last synced: about 1 year ago - Pushed: about 5 years ago - Stars: 3 - Forks: 0

chmod775/trace

Electronic PCB Programmig Language: Create an Electronic Netlist and Schematic using JavaScript and limitless automations.

Language: JavaScript - Size: 440 KB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 3 - Forks: 0

SubZer0811/BE2SIM

This repository contains a python script that converts a Boolean Expression to a .SIM file (circuit netlist description).

Language: Python - Size: 4.88 KB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 3 - Forks: 0

JensRestemeier/EdifTests

A few experiments using the SpyDrNet netlist library.

Language: Python - Size: 7.81 KB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 0 - Forks: 0

CIDARLAB/miniFluigi

A more modular Fluigi Codebase

Language: Java - Size: 455 KB - Last synced: 4 months ago - Pushed: over 4 years ago - Stars: 0 - Forks: 0

CIDARLAB/MINT

Language: ANTLR - Size: 32.2 KB - Last synced: 4 months ago - Pushed: over 6 years ago - Stars: 5 - Forks: 3