GitHub topics: netlist

Repositories

najaeda/naja

Structural Netlist API (and more) for EDA post synthesis flow development

Language: Verilog - Size: 16.2 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 113 - Forks: 18

google/pcbdl 📦

PCB Design Language: A programming way to design schematics.

Language: Python - Size: 6.12 MB - Last synced at: 4 days ago - Pushed at: over 4 years ago - Stars: 181 - Forks: 26

circuitgraph/circuitgraph

Tools for working with circuits as graphs in python

Language: Verilog - Size: 10.5 MB - Last synced at: 3 days ago - Pushed at: almost 2 years ago - Stars: 123 - Forks: 13

nturley/netlistsvg

draws an SVG schematic from a JSON netlist

Language: JavaScript - Size: 1.02 MB - Last synced at: 5 days ago - Pushed at: over 1 year ago - Stars: 723 - Forks: 93

emsec/hal

HAL – The Hardware Analyzer

Language: C++ - Size: 3.19 GB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 681 - Forks: 86

wiresynth/wiresynth.sc

Describing components and wiring in circuit board design with presentation in Scala.

Language: Scala - Size: 22.5 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

jellyterra/wiresynth.sc

Describing components and wiring in circuit board design with presentation in Scala.

Language: Scala - Size: 25.4 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

matth2k/safety-net

A reference-counted netlist library for EDA tool development

Language: Rust - Size: 197 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 0 - Forks: 0

circuitgraph/circuitsim

Perform gate-level simulations from python

Language: Python - Size: 44.9 KB - Last synced at: 5 days ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 0

najaeda/naja-verilog

A standalone structural (gate-level) verilog parser

Language: C++ - Size: 166 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 37 - Forks: 2

SpiceSharp/SpiceSharpParser

SPICE netlists parser for .NET

Language: C# - Size: 8.52 MB - Last synced at: 16 days ago - Pushed at: 8 months ago - Stars: 30 - Forks: 6

shishir-dey/vhdl-samples

Contains VHDL netlists of basic digital circuits

Language: VHDL - Size: 6.26 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 3 - Forks: 0

tscircuit/circuit-json-to-readable-netlist

Convert Circuit JSON into a readable netlist suitable for input to AI

Language: TypeScript - Size: 138 KB - Last synced at: 9 days ago - Pushed at: 3 months ago - Stars: 1 - Forks: 3

ganeshgore/spydrnet-physical

This is a SpyDrNet Plugin for a physical design related transformations

Language: Python - Size: 18.9 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 13 - Forks: 4

BUAA-CLab/CircuitMind

The code about TC-Bench and CircuitMind

Language: Python - Size: 1.07 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 3 - Forks: 0

byuccl/spydrnet-tmr

TMR utilities for the SpyDrNet project

Language: Python - Size: 10.7 MB - Last synced at: 8 days ago - Pushed at: almost 2 years ago - Stars: 10 - Forks: 4

byuccl/spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Language: Python - Size: 46 MB - Last synced at: 3 months ago - Pushed at: 7 months ago - Stars: 95 - Forks: 23

electron-lang/electron

A mixed signal netlist language (pre-alpha)

Language: TypeScript - Size: 2.71 MB - Last synced at: 11 days ago - Pushed at: about 7 years ago - Stars: 61 - Forks: 7

arasgungore/netlist-solver

A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit.

Language: MATLAB - Size: 531 KB - Last synced at: 5 months ago - Pushed at: about 3 years ago - Stars: 20 - Forks: 3

aaanthonyyy/CircuitNet

A hand-drawn schematic sketch recognizer and converter. Traditional object detection techniques built using OpenCV; deep learning classification powered by TensorFlow 2 using the Keras API.

Language: Jupyter Notebook - Size: 44.6 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 33 - Forks: 5

This project showcases the design and simulation of a 7T MCPL SRAM using adiabatic logic for low-power efficiency, developed for ECL 312 at IIIT Nagpur. It compares the 6T and 7T SRAM designs in terms of power, energy, and stability, with simulations done in WinSpice and Microwind.

Language: SystemVerilog - Size: 3.62 MB - Last synced at: 2 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

firechip/pads-layout-parser

Library for parsing netlists in the PADS Layout ASCII format (`.asc` files). It provides a structured object representation of the netlist data, making it easy to process and convert to other formats like the Yosys JSON format used for circuit analysis and visualization.

Language: TypeScript - Size: 113 KB - Last synced at: 9 days ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

akashlevy/pyxbar

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

Language: SourcePawn - Size: 184 MB - Last synced at: 11 days ago - Pushed at: over 5 years ago - Stars: 13 - Forks: 4

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Language: VHDL - Size: 46.9 KB - Last synced at: 6 months ago - Pushed at: almost 2 years ago - Stars: 8 - Forks: 2

rohankalbag/logic-simulator

Course Assignment - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay

Language: Jupyter Notebook - Size: 95.7 KB - Last synced at: 3 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

emsec/hal-benchmarks

Benchmark suite for HAL

Language: VHDL - Size: 9.16 MB - Last synced at: 6 months ago - Pushed at: almost 5 years ago - Stars: 11 - Forks: 1

muhammadtalhasami/openlane

This is my openlane repository in which we perform synthesis of our design/module.

Language: Tcl - Size: 384 KB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

pablov55/Beginner-s-Guide-to-KiCad

This guide will teach you all the basics of KiCad from schematic building to PCB design. It will also teach you how to add libraries, create your own symbols & footprints, export the drill and gerber files, and many more tips to get you started on your KiCad journey!

Language: HTML - Size: 5.29 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

netlist 41 verilog 12 eda 9 python 8 fpga 7 kicad 6 hardware 6 vhdl 5 edif 4 pcb 4 netlists 4 schematic 4 hdl 4 spice 4 netlist-parser 3 circuits 3 electronic-design-automation 3 circuit 3 electronics 3 parser 3 hardware-designs 3 circuit-design 3 spydrnet 3 testbench 2 automation 2 computer-aided-design 2 digital 2 fpgas 2 transformation 2 transformations 2 cad 2 circuit-analysis 2 netlist-simulator 2 fault-injection 2 openlane 2 vivado 2 simulation 2 boolean-circuits 2 microfluidics 2 schematics 2 cpp 2 semiconductor 2 reverse-engineering 2 asic 2 openlane-github- 1 pcb-layouts 1 pcb-manufacturing 1 computer-engineering 1 computer-science 1 engineering 1 nexys4 1 thesis 1 capacitance 1 delay 1 fall-delay 1 fall-time 1 gate-delay 1 inverter-sizing 1 ltspice 1 propagation-delay 1 rise-delay 1 rise-time 1 openlanegithub- 1 placement- 1 rounting- 1 synthesis 1 footprint-libraries 1 gerber 1 gerber-files 1 kicad-3dmodels 1 kicad-footprints 1 kicad-libraries 1 kicad-library 1 kicad-pcb 1 kicad-pcb-wiring 1 kicad-project 1 kicad-schematics 1 kicad-symbols 1 pcb-design 1 pcb-designing 1 pcb-footprints 1 pcb-layout 1 sizing 1 turing-machine-simulator 1 fluigi 1 sim-file 1 modnet 1 postfix 1 irsim 1 circuit-netlist-description 1 pip 1 boolean-expression 1 synplify-pro 1 circuits-and-electronics 1 microcontroller-boards 1 pyqt5 1 javascript 1 liberty 1 wizard 1 terminal-based 1