GitHub topics: netlist-parser
najaeda/naja-verilog
A standalone structural (gate-level) verilog parser
Language: C++ - Size: 196 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 35 - Forks: 2
arasgungore/netlist-solver
A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit.
Language: MATLAB - Size: 531 KB - Last synced at: 12 days ago - Pushed at: over 2 years ago - Stars: 20 - Forks: 3
byuccl/spydrnet
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
Language: Python - Size: 46 MB - Last synced at: 8 months ago - Pushed at: about 1 year ago - Stars: 88 - Forks: 21
gabrielseibel1/BINS
BINS Is Not SPICE: a SPICE-inspired circuit simulator.
Language: C++ - Size: 1.27 MB - Last synced at: 2 months ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 1
