Pranavh-2004/64KB_RAM_iverilog

PESU Sem 3: Mini project for Digital Design and Computer Organization

Language: Verilog - Size: 259 KB - Last synced at: 3 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

akashlevy/pyxbar

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

Language: SourcePawn - Size: 184 MB - Last synced at: 6 days ago - Pushed at: over 5 years ago - Stars: 13 - Forks: 4

AkhilRai28/Single-Port-RAM

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

Language: Verilog - Size: 68.4 KB - Last synced at: 2 months ago - Pushed at: 10 months ago - Stars: 3 - Forks: 0

AhmedIssa11/Compiler-Design

Language: C# - Size: 1.87 MB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 4 - Forks: 1