GitHub / AkhilRai28 / Single-Port-RAM

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AkhilRai28%2FSingle-Port-RAM
PURL: pkg:github/AkhilRai28/Single-Port-RAM

Topics: digital-circuits, fpga, fpga-programming, hardware, hardware-description-language, memory-design, ram, single-port, synchronous, testbench, verilog

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