xrddev/circuit-reliability-testing

VHDL circuit testing project featuring scan-based TRCUT architecture with testbenches, LFSR-based pseudorandom input generation, MISR-based signature analysis with fault injection (stuck-at and transient), and full IEEE 1149.1 (JTAG) implementation with TAP controller and boundary scan.

Language: VHDL - Size: 9.38 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 0 - Forks: 0

UTehran-NavabiLab/SAYAC-system-Testing

Post-manufacturing test analysis

Language: VHDL - Size: 8.72 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Manarabdelaty/Fault-SPM

SPM with DFT structure automatically injected by Fault

Language: Verilog - Size: 30.3 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 1

celine-hsieh/VLSI-Testing-LAB-2

Language: Verilog - Size: 1.84 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0