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GitHub topics: fault-modeling

Mummanajagadeesh/4-bit-ripple-carry-adder

VLSI test project: 4-bit ripple carry adder with random stuck-at fault injection. Supports ATPG-based verification, fault modeling, and simulation for learning and experimentation

Language: Python - Size: 9.77 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

virtualsatellite/VirtualSatellite4-FDIR

Virtual Satellite 4 - FDIR Application

Language: Java - Size: 28.1 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 6 - Forks: 0

Related Keywords
fault-modeling 2 atpg 1 hdl 1 icarus 1 simulation 1 stuck-at-faults 1 testing 1 verilog 1 vlsi 1 vlsi-testing 1 vlsi-verification 1 dlr 1 eclipse 1 fdir 1 virtualsatellite 1