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GitHub topics: ml-for-logic-synthesis

NYU-MLDA/ABC-RL

This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.

Language: Verilog - Size: 21.1 MB - Last synced: 24 days ago - Pushed: 24 days ago - Stars: 1 - Forks: 0

Related Keywords
abc-rl 1 boolean-circuit-minimization 1 boolean-optimization 1 deep-learning 1 electronic-design 1 electronic-design-automation 1 iclr2024 1 logic-synthesis 1 mcts 1 mcts-agents 1 ml-for-chip-design 1 ml-for-logic-synthesis 1 reinforcement-learning 1 retrieval-guided-rl 1