reedalexander490/4x4-Multiplier

Language: Verilog - Size: 11.7 KB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 0 - Forks: 0

abdelazeem201/ASIC-Implementation-UART

This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from system clock. If we increase the baud rate, speed of serial data transmission increases. As the dividing factor decrease baud rate increases. in this paper we set the system clock frequency as 50MHz and time to transfer each data bit is 23.75ns with baud rate of 42.1 Mbps (dividing factor is 32). Due to increase in the baud rate the time taken to transfer the data decreases, so it is very useful for faster communication devices. Transmitter and Receiver blocks designed by algorithm state machine method simulated in ModelSim, synthesized in Design Compiler, and extracted in ICC in Nangate 45 nm CMOS cell library.

Language: Verilog - Size: 9.09 MB - Last synced at: 20 days ago - Pushed at: about 3 years ago - Stars: 11 - Forks: 5

US-CBP/GTAS

Global Travel Assessment System | A passenger data screening and analysis system for enhancing global security

Language: Java - Size: 96.1 MB - Last synced at: 27 days ago - Pushed at: over 1 year ago - Stars: 119 - Forks: 78

abdelazeem201/ICC2_scripts

This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.

Language: Tcl - Size: 303 KB - Last synced at: 20 days ago - Pushed at: about 1 year ago - Stars: 16 - Forks: 1

m1x0n/easy-pnr-api-php

PHP API Client for EasyPNR Decoder

Language: PHP - Size: 16.6 KB - Last synced at: about 2 months ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

efabless/openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

Language: Python - Size: 31.4 MB - Last synced at: about 2 months ago - Pushed at: 2 months ago - Stars: 272 - Forks: 54

RAJIV81205/Easy-Rail

Language: JavaScript - Size: 664 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0

abdelazeem201/RV32E201X

RV32E201X is a 5-stage pipelined 32-bit RISC-V processor core.

Language: Verilog - Size: 20.5 MB - Last synced at: 20 days ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 3

ghdl/docker

Scripts to build and use docker images including GHDL

Language: Shell - Size: 250 KB - Last synced at: 19 days ago - Pushed at: 5 months ago - Stars: 42 - Forks: 11

Li-Yueting/aloe-sky130

Language: Verilog - Size: 209 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0

kholoud0/ASIC-Implementauion-of-CV32E40S-RISC-V-core-

This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).

Language: SystemVerilog - Size: 84.5 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0

porglezomp/minecraft-eda

Electronic design automation for Minecraft

Language: Python - Size: 7.81 KB - Last synced at: 27 days ago - Pushed at: almost 6 years ago - Stars: 9 - Forks: 0

basemhesham/Design-and-ASIC-Implementation-of-UART

This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II

Language: Verilog - Size: 1020 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 3 - Forks: 0

mohamedtareq24/ASIC_implementation_of_PULPino_SoC

My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools

Language: Verilog - Size: 21.9 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

mohamedtareq24/ASICs_Design_Diploma

RTL to GDSII flow of a low Power configurable multi clock digital system

Language: Verilog - Size: 31.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

vipulwairagade/get-pnr-status

Get Coach, Birth Number and Status from your PNR number

Language: Python - Size: 1000 Bytes - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 1

abdelazeem201/DTMF

Design and Implementation of Goertzel Algorithm for DTMF application on ASIC.

Language: Verilog - Size: 469 KB - Last synced at: 20 days ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 1

vsdip/avsdmux2x1_3v3

Language: Shell - Size: 2.59 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

crackCodeLogn/PNR_Enquiry_IndianRailways_v2.0

This project caters to the extraction of the status of PNR number (Passenger Name Record) of Indian Railways. PNR number is unique to each and every ticket bought in the railways. With the help of it, we can get the exact details of the ticket in hand

Language: Java - Size: 860 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

crackCodeLogn/PNR_Enquiry_IndianRailways

This project caters to the extraction of the status of PNR number (Passenger Name Record) of Indian Railways. PNR number is unique to each and every ticket bought in the railways. With the help of it, we can get the exact details of the ticket in hand

Language: Java - Size: 452 KB - Last synced at: almost 2 years ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 1

sangamcse/myPNRStatus

A script in python3 to check PNR status on your terminal

Language: Python - Size: 5.86 KB - Last synced at: about 1 month ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

praveenpuglia/railly

First Class, Indian Railways Experience

Language: Vue - Size: 90.8 KB - Last synced at: 27 days ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0