Ecosyste.ms: Repos
An open API service providing repository metadata for many open source software ecosystems.
GitHub topics: place-and-route
PokeyMystery/SerDes-Design-UVM-and-Physical-Design
SerDes RTL design, verification using UVM and Physical design.
Language: Verilog - Size: 1.21 MB - Last synced: 17 days ago - Pushed: 19 days ago - Stars: 0 - Forks: 0
SingularityKChen/langchain-vlsi-flow
LangChain based VLSI flow that is able to generate required HDL, testbench, design creation and implementaion scripts.
Language: Makefile - Size: 355 KB - Last synced: 11 months ago - Pushed: 11 months ago - Stars: 1 - Forks: 0
NikosDelijohn/LAP
Lark based DEF file parser
Language: Python - Size: 3.1 MB - Last synced: 12 months ago - Pushed: 12 months ago - Stars: 2 - Forks: 0
jasonlin316/RISC-V-CPU
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
Language: Verilog - Size: 20.2 MB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 54 - Forks: 15
porglezomp/minecraft-eda
Electronic design automation for Minecraft
Language: Python - Size: 7.81 KB - Last synced: about 1 year ago - Pushed: about 5 years ago - Stars: 4 - Forks: 0
SymbiFlow/vtr-verilog-to-routing Fork of verilog-to-routing/vtr-verilog-to-routing
SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
Language: C++ - Size: 139 MB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 34 - Forks: 12
Werni2A/Valhalla-II
Open-Source VHDL Synthesis for Alhambra II FPGA Board
Language: VHDL - Size: 19.5 KB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 3 - Forks: 2
