GitHub topics: gate-level
KrishanuDevSarma/Approximate-Comparator-Designs-for-Area-Efficient-Digital-Systems
Area-efficient approximate comparators (4–32 bit) with Verilog RTL, testbenches, and analysis.
Language: Verilog - Size: 248 KB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 0 - Forks: 0
jasonlin316/RISC-V-CPU
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
Language: Verilog - Size: 20.2 MB - Last synced at: 7 months ago - Pushed at: over 5 years ago - Stars: 119 - Forks: 27
cad-polito-it/fenice
Customizable fault-simulation and gate-level editing library for sequential circuits
Language: C - Size: 1.03 MB - Last synced at: 12 months ago - Pushed at: about 4 years ago - Stars: 6 - Forks: 1
alirezajaberirad/Object-Oriented-Modeling-of-Electronic-Circuits
This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022
Language: C++ - Size: 7.06 MB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0
Archfx/TrojanWars
TrojanWars🐎 - Test Generation for activation of malicious hardware implants
Language: C - Size: 53.8 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
gonsie/gates
Gate-level circuit model for ROSS
Language: C - Size: 41.9 MB - Last synced at: 6 days ago - Pushed at: over 5 years ago - Stars: 6 - Forks: 1
Aliiiw/Computer-Architecture-project
implement mips cpu in python
Language: Python - Size: 157 KB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 2
jasonlin316/A-Single-Path-Delay-32-Point-FFT-Processor
A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.
Language: Verilog - Size: 1.81 MB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 20 - Forks: 11
FarshidKeivanian/Optimization-of-JK-Flip-Flop-Layout-with-Minimal-Average-Power-of-Consumption-based-on-ACOR-Fuzzy-A
FuzzyACOR-Algorithm (Adaptive fuzzy metaheuristic based optimisation algorithm)
Language: MATLAB - Size: 1.06 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 1
FPGA-Systems/gate_level
Реализация элементов цифровых схем из базовых логических элементов
Language: VHDL - Size: 6.33 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
