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GitHub / verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/verilog-to-routing%2Fvtr-verilog-to-routing

Stars: 962
Forks: 372
Open Issues: 466

License: other
Language: C++
Repo Size: 291 MB
Dependencies: 0

Created: almost 9 years ago
Updated: about 20 hours ago
Last pushed: about 22 hours ago
Last synced: about 20 hours ago

Topics: cad, eda, fpga, placement, routing, synthesis, verilog, vpr, vtr

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