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GitHub / verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/verilog-to-routing%2Fvtr-verilog-to-routing

Stars: 1,103
Forks: 415
Open issues: 250

License: other
Language: C++
Size: 319 MB
Dependencies parsed at: Pending

Created at: almost 10 years ago
Updated at: 9 days ago
Pushed at: 9 days ago
Last synced at: 9 days ago

Topics: cad, eda, fpga, placement, routing, synthesis, verilog, vpr, vtr

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