GitHub / verilog-to-routing / vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
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PURL: pkg:github/verilog-to-routing/vtr-verilog-to-routing
Stars: 1,160
Forks: 430
Open issues: 154
License: other
Language: C++
Size: 351 MB
Dependencies parsed at: Pending
Created at: over 10 years ago
Updated at: 6 days ago
Pushed at: 6 days ago
Last synced at: 6 days ago
Topics: cad, eda, fpga, placement, routing, synthesis, verilog, vpr, vtr
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