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GitHub / verilog-to-routing / vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Stars: 962
Forks: 373
Open Issues: 466
License: other
Language: C++
Repo Size: 291 MB
Dependencies:
0
Created: almost 9 years ago
Updated: 5 days ago
Last pushed: 10 days ago
Last synced: 10 days ago
Topics: cad, eda, fpga, placement, routing, synthesis, verilog, vpr, vtr
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