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GitHub / verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/verilog-to-routing%2Fvtr-verilog-to-routing

Stars: 1,106
Forks: 415
Open issues: 193

License: other
Language: C++
Size: 320 MB
Dependencies parsed at: 0

Created at: almost 10 years ago
Updated at: 1 day ago
Pushed at: about 6 hours ago
Last synced at: about 6 hours ago

Topics: cad, eda, fpga, placement, routing, synthesis, verilog, vpr, vtr

No dependencies found