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GitHub / verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/verilog-to-routing%2Fvtr-verilog-to-routing

Stars: 1,086
Forks: 411
Open issues: 479

License: other
Language: C++
Size: 313 MB
Dependencies parsed at: Pending

Created at: almost 10 years ago
Updated at: 3 days ago
Pushed at: 1 day ago
Last synced at: 1 day ago

Topics: cad, eda, fpga, placement, routing, synthesis, verilog, vpr, vtr

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