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GitHub / animeshbchowdhury / RTL_dataset
Extract leaf level RTL modules from OpenROAD and collect PPA numbers generated by Yosys
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/animeshbchowdhury%2FRTL_dataset
Stars: 0
Forks: 0
Open Issues: 0
License: bsd-3-clause
Language: Verilog
Repo Size: 6.92 MB
Dependencies: pending
Created: 3 months ago
Updated: 3 months ago
Last pushed: 3 months ago
Last synced: 3 months ago
Topics: electronics-design, electronics-design-automation, labeled-data, logic-synthesis