GitHub topics: gdsii-flow
Pratim-Senapati/qflow-projects
A complete setup for Qflow, an open-source digital VLSI design flow. This repo provides pre-configured example projects, automated installation scripts, and step-by-step instructions to synthesize, place, and route Verilog designs into GDSII layouts. Supports both running example designs and using your own Verilog.
Language: Python - Size: 7.85 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 0 - Forks: 0
abdelazeem201/OpenLane Fork of The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Size: 833 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0
