GitHub / DuttPanchal04 / rtl-design-and-synthesis-using-icarus-verilog-gtkwave-yosys

A collection of Verilog-based RTL design projects with testbenches, simulated using Icarus Verilog and GTKWave. This repo showcases foundational digital logic circuits as part of my VLSI learning journey using open-source tools.

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Topics: digital-logic, gtkwave, hdl, icarus, open-source, rtl, synthesis, testbench, verification, verilog, vlsi-design, yosys

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• Readme
• Dependencies