GitHub / gabrielganzer / VHDL-DesignSynthesis
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/gabrielganzer%2FVHDL-DesignSynthesis
PURL: pkg:github/gabrielganzer/VHDL-DesignSynthesis
Stars: 4
Forks: 0
Open issues: 0
License: bsd-2-clause
Language: Verilog
Size: 7.4 MB
Dependencies parsed at: Pending
Created at: over 4 years ago
Updated at: about 2 years ago
Pushed at: over 4 years ago
Last synced at: about 2 years ago
Topics: adder-subtractor, booth-multiplier, control-unit, digital-design, physical-design, polito, register-file, rtl, scripts, subtractor, synthesis, tcl, verilog, vhdl, windowed-register-file