GitHub / RISC-Processor / Pipelined-Processor
5-Stage Pipelined Processor for RV32I with Hazard Control and Branch Prediction.
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PURL: pkg:github/RISC-Processor/Pipelined-Processor
Stars: 0
Forks: 1
Open issues: 0
License: None
Language: Verilog
Size: 55.5 MB
Dependencies parsed at: Pending
Created at: 6 months ago
Updated at: 2 months ago
Pushed at: 2 months ago
Last synced at: 2 months ago
Topics: pipelined-processor, processor-design, risc-v
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