jorgeloopzz/Multiplier

Language: VHDL - Size: 985 KB - Last synced at: about 20 hours ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

Jjateen/Snake-Game-Verilog

This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

Language: Verilog - Size: 8.63 MB - Last synced at: 3 months ago - Pushed at: 4 months ago - Stars: 2 - Forks: 0

dan-lara/FPGA-Ultrasonic-2D-Radar

Language: C - Size: 21.5 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

WassimHedfi/FPGA_ADC_PWM_MotorControl

This repository contains the implementation of a motor speed control system using an FPGA. The speed is adjusted dynamically through a potentiometer, leveraging ADC for analog-to-digital conversion and PWM for precise motor control.

Language: Verilog - Size: 1.05 MB - Last synced at: 2 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

JosiahMendes/Autonomous-Rover

The Design and Implementation of an Autonomous Mars Rover that has full mapping, remote control and power management capabilities.

Language: C - Size: 396 MB - Last synced at: 10 days ago - Pushed at: almost 4 years ago - Stars: 10 - Forks: 3

JoaoSilvaIT/Integer-Multiplier

Project made in my 1st year at University using Structural VHDL to implement a 4 bit integer multiplier using the MAX DE10-Lite Board

Language: VHDL - Size: 5.24 MB - Last synced at: 2 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

franciscoengenheiro/ticket-machine-fpga

Train ticket vending machine application designed for execution on an FPGA system. The application allows users to purchase tickets for various destinations and includes maintenance functionalities.

Language: Kotlin - Size: 10.8 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0

naresh0902/Washing_Machine_Controller

A Control System for Washing Machine in Verilog HDL and DE10 Lite Board

Language: Verilog - Size: 4.42 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

pa-tiq/vending_machine

Language: Verilog - Size: 8.87 MB - Last synced at: over 1 year ago - Pushed at: almost 6 years ago - Stars: 5 - Forks: 3

jakujobi/BitBlaster_10bit_Processor

Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.

Language: SystemVerilog - Size: 181 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

austindriggs/wvu-cpe271

Design of a Simple CPU using the DE10-Lite FPGA from Intel and Quartus Prime

Language: VHDL - Size: 6.69 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

realchonk/quartus-make

This is a template for projects using the Quartus Prime suite with the DE10-Lite FPGA board.

Language: Verilog - Size: 15.6 KB - Last synced at: 10 months ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 0

tanb01/MLED

VHDL Project 2018-2019: A university project to discover VHDL and the DE10 LITE 10M50DAF484C7G, just a "Moving Light Emitting Diode". The changing LED states between 10 LEDS creating the illusion that one LED is moving.

Language: VHDL - Size: 9.77 KB - Last synced at: over 1 year ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 0

LockBall/floatfixlib_VHDL1993

ieee_proposed with names changed to floatfixlib to be compatible with Quartus Prime Lite and support fixed, float, etc.

Language: VHDL - Size: 111 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

RomeoMe5/De10-Lite_HDL_GPS

Simple verilog project with ability to connect to GPS module using UART and parse NMEA coordinates using finite state machine

Language: Verilog - Size: 2.19 MB - Last synced at: over 1 year ago - Pushed at: about 6 years ago - Stars: 7 - Forks: 6

Jideco/PongGameGroup22

This is a Pong Game created by Group 22 for EEE308 project, Electronics and Electrical Department, Obafemi Awolowo University.

Language: VHDL - Size: 5.52 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

protocol66/FPGADefender

VHDL implementation of the Defender arcade game for DE-10 Lite FPGA. For ECE 4110 project.

Language: VHDL - Size: 38.8 MB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 1

trilogysci/xasted

A 6 x 7 segment shooter game for fpga (DE10-Lite)

Language: Verilog - Size: 22.5 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

aileneiioana/NiosII_HDL

Language: Verilog - Size: 215 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

FedorChervyakov/de10lite-hello-vga

VGA demo on the Terasic DE10-Lite FPGA board

Language: VHDL - Size: 48.8 KB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 4

RomeoMe5/Terasic-SMK-driver-use-cases

Terasic Servo Motor Kit (SMK) usage examples

Size: 16.6 KB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 0

DavidKopalaCU/Verilog-ReactionTimer

A Reaction Timer for the DE10 Lite FPGA Written in Verilog HDL

Language: Verilog - Size: 5.46 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 1

NestorDP/Verilog_by_examples

Source codes of examples from the book Verilog by Examples

Language: Verilog - Size: 64.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

timot3/ECE385-Ethernet

ECE 385 Final Project -- Ethernet on MAX10 DE10-Lite FPGA and Nios II soft processor

Language: Verilog - Size: 35.4 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 7 - Forks: 0

JorgeAskur/Tic-Tac-Toe-FPGA

A recreation of the popular game Tic-Tac-Toe for the DE10-Lite FPGA dev board, in VHDL.

Language: VHDL - Size: 4.86 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0

FedorChervyakov/de10lite-hello-adc

ADC demo on the Terasic DE10-Lite board with MAX10 FPGA

Size: 31.3 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1

jeferal/Pong-FPGA

Pong game on FPGA Max 10 DE10-Lite, written in VHDL.

Language: VHDL - Size: 337 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 7 - Forks: 6

w3arycod3r/fpga-defender

A recreation of Williams Defender 1981 arcade game for DE10-Lite FPGA dev board, written in VHDL.

Language: VHDL - Size: 7.44 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 14 - Forks: 4

kodachi77/DE10liteDhrystone

Nios II Embedded System Dhrystone Test

Language: C - Size: 1.31 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

FedorChervyakov/de10lite-hello-nios2

Hello World from Nios 2

Language: Tcl - Size: 66.4 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 1