GitHub / vinayak1998 / 7-segment-display-fpga
Design and implement a Seven Segment Display available on the BASYS3 board (FPGA) in VHDL
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Stars: 2
Forks: 0
Open issues: 0
License: None
Language: VHDL
Size: 455 KB
Dependencies parsed at: Pending
Created at: over 7 years ago
Updated at: over 1 year ago
Pushed at: over 7 years ago
Last synced at: over 1 year ago
Topics: fpga, vhdl, xilinx, xilinx-fpga, xilinx-ise, xilinx-vivado
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