GitHub / RipperJ / VerilogExpr2NAND-NOR
Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation
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Stars: 3
Forks: 0
Open issues: 0
License: mit
Language: Python
Size: 42 KB
Dependencies parsed at: Pending
Created at: over 2 years ago
Updated at: about 2 years ago
Pushed at: almost 2 years ago
Last synced at: almost 2 years ago
Topics: boolean-expression, compiler, espresso, lex, logic-minimization, nand, nor, ply, pyeda, simulation, verilog, vivado-simulator, xsim, yacc
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