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GitHub / meiniKi / FazyRV

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meiniKi%2FFazyRV

Stars: 60
Forks: 1
Open Issues: 0

License: None
Language: SystemVerilog
Repo Size: 764 KB
Dependencies: 41

Created: 3 months ago
Updated: 8 days ago
Last pushed: 8 days ago
Last synced: 7 days ago

Topics: computer-architecture, digital-design, embedded-systems, fpga, risc-v, system-on-chip, vlsi-design

Files
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    Readme
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    Dependencies
    .github/workflows/impl.yml actions
    .github/workflows/lint.yml actions
    .github/workflows/setup-riscv-toolchain/action.yml actions
    .github/workflows/setup-sail/action.yml actions
    .github/workflows/track_area.yml actions
    .github/workflows/verif.yml actions
    requirements.txt pypi