GitHub / AnjanaSenanayake / verilog-model-for-8bit-processor
An implementation of a processor with basic components coded in verilog
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PURL: pkg:github/AnjanaSenanayake/verilog-model-for-8bit-processor
Stars: 2
Forks: 2
Open issues: 0
License: None
Language: Verilog
Size: 6.84 KB
Dependencies parsed at: Pending
Created at: almost 8 years ago
Updated at: 7 months ago
Pushed at: almost 8 years ago
Last synced at: 4 months ago
Topics: alu, computer-architecture, digital-design, opcode, processor, register, verilog, verilog-hdl
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