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GitHub / eshansurendra / UART-FPGA

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/eshansurendra%2FUART-FPGA
PURL: pkg:github/eshansurendra/UART-FPGA

Stars: 1
Forks: 0
Open issues: 0

License: None
Language: SystemVerilog
Size: 3.5 MB
Dependencies parsed at: Pending

Created at: about 1 year ago
Updated at: about 1 year ago
Pushed at: about 1 year ago
Last synced at: 4 months ago

Commit Stats

Commits: 7
Authors: 2
Mean commits per author: 3.5
Development Distribution Score: 0.429
More commit stats: https://commits.ecosyste.ms/hosts/GitHub/repositories/eshansurendra/UART-FPGA

Topics: digital-design, embedded-systems, fpga, quartus-prime, systemverilog-hdl, testbench, uart, verilog

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