GitHub / MohamedHussein27 / SPI_Slave_With_Single_Port_Memory
This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with sigle port sync RAM. The project includes the design and code for an SPI Slave, a single-port asynchronous RAM, and an SPI Wrapper that connects the RAM and SPI Slave.
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PURL: pkg:github/MohamedHussein27/SPI_Slave_With_Single_Port_Memory
Stars: 5
Forks: 0
Open issues: 0
License: None
Language: Verilog
Size: 2.18 MB
Dependencies parsed at: Pending
Created at: about 1 year ago
Updated at: 6 months ago
Pushed at: 6 months ago
Last synced at: 6 months ago
Topics: digital-design, fsm, spi-interface, tcltk, verilog-hdl, verilog-project, vivado