GitHub / geitanksha / risc-v-pipelined
Created a RISC-V Pipelined processor in SystemVerilog with features like Caches, Prefetching, History Table. Skills employed: SystemVerilog, Verdi, Logic Design, Computer Architecture
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PURL: pkg:github/geitanksha/risc-v-pipelined
Stars: 0
Forks: 0
Open issues: 0
License: None
Language: HTML
Size: 5.43 MB
Dependencies parsed at: Pending
Created at: over 2 years ago
Updated at: about 2 years ago
Pushed at: about 2 years ago
Last synced at: about 2 years ago
Topics: computer-architecture, logic-design, systemverilog, verdi