GitHub / siidheesh / EE2020

EE2020 AY16/17 Design Project: FPGA-based Digital Signal Generator

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PURL: pkg:github/siidheesh/EE2020

Stars: 3
Forks: 0
Open issues: 0

License: gpl-3.0
Language: VHDL
Size: 62.2 MB
Dependencies parsed at: Pending

Created at: over 8 years ago
Updated at: over 1 year ago
Pushed at: over 8 years ago
Last synced at: over 1 year ago

Topics: basys, ee2020, fpga, nus, verilog, xil, xilinx

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