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GitHub / tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tymonx%2Flogic
Stars: 248
Forks: 53
Open Issues: 0
License: apache-2.0
Language: SystemVerilog
Repo Size: 820 KB
Dependencies:
0
Created: over 6 years ago
Updated: 3 months ago
Last pushed: over 4 years ago
Last synced: 2 months ago
Topics: asic, cmake, cpp, fpga, hdl, modelsim, quartus, rtl, systemc, systemverilog, testing-rtl, unit-tests, uvm, verification, verilator, verilog, vivado, xilinx
Files
No dependencies found