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GitHub / shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK
This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified
Stars: 26
Forks: 7
Open Issues: 0
License: None
Language: Verilog
Repo Size: 44.9 MB
Dependencies: pending
Created: almost 3 years ago
Updated: 12 months ago
Last pushed: almost 3 years ago
Last synced: 12 months ago
Topics: electronics-engineering, risc-v, vlsi-physical-design