GitHub / SauravMaheshkar / verilog-template
❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SauravMaheshkar%2Fverilog-template
PURL: pkg:github/SauravMaheshkar/verilog-template
Stars: 1
Forks: 0
Open issues: 2
License: mit
Language: Makefile
Size: 15.6 KB
Dependencies parsed at: Pending
Created at: over 1 year ago
Updated at: 12 months ago
Pushed at: 12 months ago
Last synced at: 5 days ago
Topics: hardware-description-language, template-project, verilog, verilog-template, vhdl
Funding Links https://github.com/sponsors/SauravMaheshkar