GitHub topics: systemrdl-compiler
SystemRDL/systemrdl-compiler
SystemRDL 2.0 language compiler front-end
Language: C++ - Size: 2.53 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 255 - Forks: 74

SystemRDL/PeakRDL-html
Generate address space documentation HTML from compiled SystemRDL input
Language: JavaScript - Size: 5.56 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 54 - Forks: 19

SystemRDL/PeakRDL-ipxact
Import and export IP-XACT XML register models
Language: Python - Size: 148 KB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 34 - Forks: 16

SystemRDL/PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Language: Python - Size: 918 KB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 66 - Forks: 47

SystemRDL/PeakRDL
Control and status register code generator toolchain
Language: Python - Size: 141 KB - Last synced at: 10 days ago - Pushed at: about 1 month ago - Stars: 138 - Forks: 28

Juniper/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Language: Verilog - Size: 7.08 MB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 199 - Forks: 71

Risto97/PeakRDL-halcpp
C++ 17 Hardware abstraction layer generator from systemrdl
Language: C++ - Size: 1.23 MB - Last synced at: 16 days ago - Pushed at: 27 days ago - Stars: 12 - Forks: 6

sdnellen/open-register-design-tool Fork of Juniper/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Language: Verilog - Size: 7.16 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 15 - Forks: 3
