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GitHub topics: fpga-development

firesim/aws-fpga-firesim

AWS Shell for FireSim

Language: VHDL - Size: 357 MB - Last synced at: 11 days ago - Pushed at: 7 months ago - Stars: 13 - Forks: 8

sdnellen/open-register-design-tool Fork of Juniper/open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Language: Verilog - Size: 7.16 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 15 - Forks: 3

KarimZakzouk/AES

Design and Development of AES Encryption and Decryption Modules in Verilog HDL for AES128, AES192, and AES256 Algorithms.

Language: Verilog - Size: 24.4 KB - Last synced at: 10 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

arnav-gudibande/fpga-intro-guide

Introductory guide to building and programming FPGAs

Language: Tcl - Size: 510 KB - Last synced at: almost 2 years ago - Pushed at: almost 8 years ago - Stars: 4 - Forks: 0

Related Keywords
fpga-development 4 fpga 3 quartus-prime 1 quartus 1 modelsim 1 hdl 1 verilog-hdl 1 security 1 hardware-design 1 data-security 1 data-encryption 1 cryptography 1 algorithm-implementation 1 aes-encryption 1 aes-decryption 1 aes-256 1 aes-192 1 aes-128 1 advanced-encryption-standard 1 verilog 1 uvm 1 systemverilog 1 systemrdl-compiler 1 systemrdl 1 registers 1 register-descriptions 1 eda 1 asic-design 1 aws-fpga 1 aws-ec2 1