GitHub / OmniaMohamed12 / S-AES-Design-and-Verification-using-SystemVerilog-and-UVM
Simplified Advanced Encryption Standard (S-AES) Design and Verification Using System Verilog and UVM.
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PURL: pkg:github/OmniaMohamed12/S-AES-Design-and-Verification-using-SystemVerilog-and-UVM
Stars: 0
Forks: 0
Open issues: 0
License: None
Language: SystemVerilog
Size: 29.3 KB
Dependencies parsed at: Pending
Created at: about 1 year ago
Updated at: about 1 year ago
Pushed at: about 1 year ago
Last synced at: about 1 year ago
Topics: functional-verification, s-aes, simplified-aes, systemverilog, uvm, uvm-verification