GitHub / ubbeg2000 / uvm-testbench-sample
Sample UVM testbench for an I2C master and slave design
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Forks: 0
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License: bsd-3-clause
Language: SystemVerilog
Size: 1.66 MB
Dependencies parsed at: Pending
Created at: 2 months ago
Updated at: about 2 months ago
Pushed at: about 2 months ago
Last synced at: about 2 months ago
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