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GitHub / yuravg / uvm_tb_cross_bar
SystemVerilog UVM testbench example
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yuravg%2Fuvm_tb_cross_bar
Stars: 20
Forks: 10
Open Issues: 0
License: mit
Language: SystemVerilog
Repo Size: 223 KB
Dependencies:
0
Created: over 4 years ago
Updated: 15 days ago
Last pushed: 15 days ago
Last synced: 15 days ago
Topics: systemverilog, uvm, verification
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