GitHub topics: parallel-prefixsum
ParimalaS27/Parallel-Prefix-Adder-8bit-UE19CS206-DDCOLab
This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.
Language: Verilog - Size: 497 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 2
AdityaNG/Parallel-Prefix-Adder
Parallel Prefix Adders achieve logarithmic time complexity by means of parallelizing the operation. For an n bit prefix adder, the critical path is one xor gate, one and/or gate and log(n) modules.
Language: Verilog - Size: 1.32 MB - Last synced at: 4 days ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 1
