GitHub topics: prefix-adder
Prithvish04/processor_design_MIPS_improvements
The repository is a project to improve the baseline MIPS processor
Language: VHDL - Size: 16.6 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
ParimalaS27/Parallel-Prefix-Adder-8bit-UE19CS206-DDCOLab
This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.
Language: Verilog - Size: 497 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 2
neeraj1397/Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
Language: Verilog - Size: 653 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 6 - Forks: 2
majabojarska/verilog-prefix-adder
6-bit prefix adder implemented via Verilog HDL.
Language: Verilog - Size: 13.5 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0
