GitHub / majabojarska / verilog-prefix-adder
6-bit prefix adder implemented via Verilog HDL.
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Stars: 0
Forks: 0
Open issues: 0
License: unlicense
Language: Verilog
Size: 13.5 MB
Dependencies parsed at: Pending
Created at: about 5 years ago
Updated at: about 4 years ago
Pushed at: almost 5 years ago
Last synced at: about 2 years ago
Topics: prefix-adder, qflow, verilog
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