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GitHub / ParimalaS27 / Parallel-Prefix-Adder-8bit-UE19CS206-DDCOLab

This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ParimalaS27%2FParallel-Prefix-Adder-8bit-UE19CS206-DDCOLab

Stars: 1
Forks: 2
Open issues: 0

License: None
Language: Verilog
Size: 497 KB
Dependencies parsed at: Pending

Created at: over 4 years ago
Updated at: almost 2 years ago
Pushed at: over 4 years ago
Last synced at: almost 2 years ago

Topics: 8bit, ddco, icarus-verilog, iverilog, parallel-prefixsum, prefix, prefix-adder, verilog

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