GitHub / SNRomon27 / Combinational-Logic-Design-Using-Verilog-HDL

Basic combinational logic design using Verilog hardware description language (HDL). A step-by-step basic combinational logic design using built-in primitives. Used Vivado 2018.3 as a text editor and simulator.

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Topics: combinational-logic, digital-electronics, hdl, verilog-hdl

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