GitHub / jeras / rp32

RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jeras%2Frp32
PURL: pkg:github/jeras/rp32

Stars: 18
Forks: 4
Open issues: 1

License: apache-2.0
Language: SystemVerilog
Size: 1.25 MB
Dependencies parsed at: Pending

Created at: almost 7 years ago
Updated at: 17 days ago
Pushed at: 17 days ago
Last synced at: 17 days ago

Topics: asic, fpga, risc-v, riscv, systemverilog

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