GitHub / Raghad-alju / fsm-sequence-detector

Implement a 3-bit sequence detector for `110` using a Mealy FSM in Cadence Virtuoso. Built with TSPC D flip-flops for optimal performance. 🛠️💻

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PURL: pkg:github/Raghad-alju/fsm-sequence-detector

Topics: cadence, digital-design, finite-state-machine, mealy-machine, schematic, sequence-detection, sequence-detector, sequence-detector-11010, simulation, spectre, state-diagram, tspc, verilog, verilog-code, verilog-hdl, verilog-project, virtuoso, waveform

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