GitHub / PyHDI / Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
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PURL: pkg:github/PyHDI/Pyverilog
Stars: 716
Forks: 199
Open issues: 78
License: apache-2.0
Language: Python
Size: 701 KB
Dependencies parsed at: Pending
Created at: over 11 years ago
Updated at: 24 days ago
Pushed at: about 1 year ago
Last synced at: 24 days ago
Commit Stats
Commits: 301
Authors: 17
Mean commits per author: 17.71
Development Distribution Score: 0.12
More commit stats: https://commits.ecosyste.ms/hosts/GitHub/repositories/PyHDI/Pyverilog
Topics: code-generator, compiler, control-flow-analyzer, dataflow-analyzer, hardware, parser, python, verilog-hdl