GitHub topics: dataflow-analyzer
PyHDI/Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
Language: Python - Size: 701 KB - Last synced at: 27 days ago - Pushed at: about 1 year ago - Stars: 716 - Forks: 199

Python-based Hardware Design Processing Toolkit for Verilog HDL
Language: Python - Size: 701 KB - Last synced at: 27 days ago - Pushed at: about 1 year ago - Stars: 716 - Forks: 199