Ecosyste.ms: Repos

An open API service providing repository metadata for many open source software ecosystems.

Package Usage: actions: ghdl/setup-ghdl-ci

Easily install tip/nightly GHDL assets in GitHub Actions workflows
1 version
Latest release: over 3 years ago

View more package details: https://packages.ecosyste.ms/registries/github%20actions/packages/ghdl/setup-ghdl-ci

View more repository details: https://repos.ecosyste.ms/hosts/GitHub/repositories/ghdl%2Fsetup-ghdl-ci

Dependent Repos 32

themperek/cocotb Fork of cocotb/cocotb
Coroutine Co-simulation Test Bench
  • nightly .github/workflows/regression-tests.yml

Size: 7.37 MB - Last synced: 3 months ago - Pushed: 3 months ago

stnolting/neorv32-riscof
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  • nightly .github/workflows/main.yml

Size: 15.3 MB - Last synced: 2 days ago - Pushed: 3 days ago

marlonjames/cocotb Fork of cocotb/cocotb
Coroutine Co-simulation Test Bench
  • nightly .github/workflows/regression-tests.yml

Size: 7.1 MB - Last synced: 18 days ago - Pushed: 18 days ago

XedaHQ/xeda
Cross EDA Abstraction and Automation
  • nightly .github/workflows/ci.yml

Size: 125 MB - Last synced: 12 days ago - Pushed: 13 days ago

umarcor/ghdl-cosim Fork of ghdl/ghdl-cosim
  • master .github/workflows/Pipeline.yml

Size: 6.28 MB - Last synced: 17 days ago - Pushed: over 1 year ago

ghdl/extended-tests
  • master .github/workflows/Test.yml

Size: 1.95 MB - Last synced: about 1 month ago - Pushed: about 1 month ago

VHDL/pyVHDLModel
An abstract language model of VHDL written in Python.
  • master .github/workflows/Pipeline.yml

Size: 4.05 MB - Last synced: about 21 hours ago - Pushed: about 22 hours ago

stnolting/neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  • nightly .github/workflows/main.yml

Size: 176 KB - Last synced: 17 days ago - Pushed: 20 days ago

GMUCERG/TinyJAMBU-SCA
  • nightly .github/workflows/main.yml

Size: 3.62 MB - Last synced: about 1 month ago - Pushed: over 1 year ago

fritzbauer/litex Fork of enjoy-digital/litex
Build your hardware, easily!
  • master .github/workflows/ci.yml

Size: 15 MB - Last synced: about 1 year ago - Pushed: over 1 year ago

Hardolaf/vunit Fork of VUnit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
  • master .github/workflows/push.yml

Size: 12.8 MB - Last synced: about 1 year ago - Pushed: over 1 year ago

VUnit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
  • master .github/workflows/push.yml

Size: 14.5 MB - Last synced: 4 days ago - Pushed: 5 days ago

VHDL/VHDLDomain
A Sphinx domain providing VHDL language support.
  • master .github/workflows/Pipeline.yml

Size: 144 KB - Last synced: 17 days ago - Pushed: 5 months ago

devsaurus/t48
A cycle-accurate VHDL model for MCS-48 and UPI devices
  • nightly .github/workflows/regression.yml

Size: 2.23 MB - Last synced: about 1 year ago - Pushed: over 1 year ago

hplp/litex Fork of enjoy-digital/litex
Build your hardware, easily!
  • master .github/workflows/ci.yml

Size: 14.7 MB - Last synced: about 1 year ago - Pushed: over 1 year ago

sshuv/iicmb
  • nightly .github/workflows/hdl.yml

Size: 4.78 MB - Last synced: 3 months ago - Pushed: 3 months ago

daxzio/setup-eda
  • nightly .github/workflows/action_ghdl.yml

Size: 44.9 KB - Last synced: 5 months ago - Pushed: 5 months ago

ghdl/ghdl-cosim
Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  • master .github/workflows/Pipeline.yml

Size: 3.36 MB - Last synced: 17 days ago - Pushed: 18 days ago

chuckb/ghdl-cosim Fork of ghdl/ghdl-cosim
Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  • master .github/workflows/Pipeline.yml

Size: 5.86 MB - Last synced: about 1 year ago - Pushed: over 1 year ago

OSVVM/OsvvmLibraries
Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  • master .github/workflows/Test.yml

Size: 165 KB - Last synced: 5 days ago - Pushed: 5 days ago

GMUCERG/LWC
Development Package for the Hardware API for Lightweight Cryptography
  • nightly .github/workflows/CI.yml

Size: 20.1 MB - Last synced: 9 months ago - Pushed: about 1 year ago

metrics-ca/vunit Fork of VUnit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
  • master .github/workflows/push.yml

Size: 13.3 MB - Last synced: 4 months ago - Pushed: 4 months ago

Fatsie/cocotb Fork of cocotb/cocotb
Coroutine Co-simulation Test Bench
  • nightly .github/workflows/regression-tests.yml

Size: 6.96 MB - Last synced: about 2 months ago - Pushed: about 2 months ago

npatsiatzis/fifo_asynchronous
  • nightly .github/workflows/formal.yml
  • nightly .github/workflows/regression.yml

Size: 7.09 MB - Last synced: 7 months ago - Pushed: 7 months ago

daxzio/myhdl Fork of myhdl/myhdl
The MyHDL development repository
  • nightly .github/workflows/test_checkin.yml

Size: 12.8 MB - Last synced: 3 months ago - Pushed: 3 months ago

Paebbels/extended-tests Fork of ghdl/extended-tests
  • master .github/workflows/Test.yml

Size: 1.96 MB - Last synced: about 1 month ago - Pushed: about 1 month ago

antmicro/litex Fork of enjoy-digital/litex
Build your hardware, easily!
  • master .github/workflows/ci.yml

Size: 15.5 MB - Last synced: about 1 month ago - Pushed: about 2 months ago

dbhi/vunit Fork of VUnit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
  • master .github/workflows/push.yml

Size: 20.2 MB - Last synced: 2 months ago - Pushed: 2 months ago

umarcor/ghdl-extended-tests Fork of ghdl/extended-tests
  • master .github/workflows/Test.yml

Size: 1.94 MB - Last synced: about 4 hours ago - Pushed: about 5 hours ago

TheRakeshPurohit/litex Fork of enjoy-digital/litex
Build your hardware, easily!
  • master .github/workflows/ci.yml

Size: 16.3 MB - Last synced: about 21 hours ago - Pushed: 1 day ago

uk0/litex Fork of enjoy-digital/litex
Build your hardware, easily!
  • master .github/workflows/ci.yml

Size: 16.2 MB - Last synced: about 15 hours ago - Pushed: 1 day ago

USAFA-ECE/helloLed
A VHDL Hello World
  • nightly .github/workflows/testbench.yml

Size: 22.5 KB - Last synced: 4 months ago - Pushed: 4 months ago

npatsiatzis/gray_bin_conv
  • nightly .github/workflows/coverage.yml
  • nightly .github/workflows/regression.yml

Size: 46.9 KB - Last synced: 8 months ago - Pushed: 8 months ago

npatsiatzis/fifo_synchronous
  • nightly .github/workflows/coverage.yml
  • nightly .github/workflows/coverage_pyuvm.yml
  • nightly .github/workflows/formal.yml
  • nightly .github/workflows/regression.yml
  • nightly .github/workflows/regression_pyuvm.yml

Size: 77.1 KB - Last synced: 8 months ago - Pushed: 8 months ago

npatsiatzis/barrel_shifter
  • nightly .github/workflows/coverage.yml
  • nightly .github/workflows/formal.yml
  • nightly .github/workflows/main.yml

Size: 7.39 MB - Last synced: 7 months ago - Pushed: 7 months ago

akaeba/tinyUART
Lightweight UART core in VHDL
  • nightly .github/workflows/unittest.yml

Size: 450 KB - Last synced: about 1 year ago - Pushed: over 1 year ago

npatsiatzis/1_wire
  • nightly .github/workflows/coverage.yml
  • nightly .github/workflows/coverage_pyuvm.yml
  • nightly .github/workflows/regression.yml
  • nightly .github/workflows/regression_pyuvm.yml

Size: 64.5 KB - Last synced: 8 months ago - Pushed: 8 months ago

akaeba/generic_spi_master
Customizable multi chip select supporting Serial Peripheral Interface master.
  • nightly .github/workflows/unittest.yml

Size: 729 KB - Last synced: about 1 year ago - Pushed: over 2 years ago

martinjthompson/ghdl-hang-test
  • nightly .github/workflows/test.yaml

Size: 8.79 KB - Last synced: about 1 year ago - Pushed: over 2 years ago

AREACODE831/te6
  • master .github/workflows/VHDL.yml

Size: 7.81 KB - Last synced: about 1 year ago - Pushed: over 2 years ago

npatsiatzis/VGA
  • nightly .github/workflows/formal.yml
  • nightly .github/workflows/regression.yml

Size: 4.46 MB - Last synced: 8 months ago - Pushed: 8 months ago

jaunas/FPGA
  • nightly .github/workflows/ghdl.yml

Size: 86.9 KB - Last synced: 10 months ago - Pushed: almost 2 years ago

mrdion/neorv32 Fork of stnolting/neorv32
A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
  • nightly .github/workflows/riscv-arch-test.yml

Size: 171 MB - Last synced: 10 months ago - Pushed: almost 3 years ago

psumesh/cocotb Fork of cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  • nightly .github/workflows/benchmark.yml

Size: 6.94 MB - Last synced: 10 months ago - Pushed: 10 months ago

psumesh/cryptocores Fork of umarcor/cryptocores
cryptography ip-cores in vhdl / verilog
  • master .github/workflows/simulation.yml

Size: 221 KB - Last synced: 10 months ago - Pushed: over 3 years ago

cyril0124/cocotb Fork of cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  • nightly .github/workflows/benchmark.yml

Size: 6 MB - Last synced: 7 months ago - Pushed: 7 months ago

flexalogic/litedram Fork of enjoy-digital/litedram
Small footprint and configurable DRAM core
  • master .github/workflows/ci.yml

Size: 1.95 MB - Last synced: 6 months ago - Pushed: 6 months ago

riktw/litex Fork of enjoy-digital/litex
Build your hardware, easily!
  • master .github/workflows/ci.yml

Size: 15.3 MB - Last synced: 10 months ago - Pushed: 10 months ago

teobiton/cocotb Fork of cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  • nightly .github/workflows/benchmark.yml

Size: 7.32 MB - Last synced: 3 days ago - Pushed: 4 days ago

rowanG077/litex Fork of enjoy-digital/litex
Build your hardware, easily!
  • master .github/workflows/ci.yml

Size: 15.4 MB - Last synced: 25 days ago - Pushed: 8 months ago

josuah/litex Fork of enjoy-digital/litex
Build your hardware, easily!
  • master .github/workflows/ci.yml

Size: 15.5 MB - Last synced: 8 months ago - Pushed: 8 months ago

abdelazeem201/OsvvmLibraries Fork of OSVVM/OsvvmLibraries
Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  • master .github/workflows/Test.yml

Size: 151 KB - Last synced: 10 months ago - Pushed: 11 months ago

Louadria/OsvvmLibraries Fork of OSVVM/OsvvmLibraries
Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  • master .github/workflows/Test.yml

Size: 153 KB - Last synced: 10 months ago - Pushed: 10 months ago

cassebas/spi-fpga Fork of jakubcabal/spi-fpga
SPI master and SPI slave for FPGA written in VHDL
  • nightly .github/workflows/main.yml

Size: 2.79 MB - Last synced: 10 months ago - Pushed: about 2 years ago

kshitij-r/vunit Fork of VUnit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
  • master .github/workflows/push.yml

Size: 14.1 MB - Last synced: 9 months ago - Pushed: about 1 year ago

jeinstei/cocotb Fork of cocotb/cocotb
Coroutine Co-simulation Test Bench
  • nightly .github/workflows/regression-tests.yml

Size: 5.69 MB - Last synced: 9 months ago - Pushed: over 3 years ago

npatsiatzis/recirculation_mux
  • nightly .github/workflows/coverage.yml
  • nightly .github/workflows/coverage_pyuvm.yml
  • nightly .github/workflows/regression.yml
  • nightly .github/workflows/regression_pyuvm.yml

Size: 10.6 MB - Last synced: 7 months ago - Pushed: 7 months ago

NicholasFengTW/spi-fpga Fork of jakubcabal/spi-fpga
SPI master and SPI slave for FPGA written in VHDL
  • nightly .github/workflows/main.yml

Size: 2.78 MB - Last synced: 9 months ago - Pushed: about 3 years ago

NicholasFengTW/eSpiMasterBfm Fork of akaeba/eSpiMasterBfm
Bus functional model of an Enhanced Serial Peripheral Interface (eSPI) master
  • nightly .github/workflows/unittest.yml

Size: 286 KB - Last synced: 9 months ago - Pushed: almost 2 years ago

joachimcao/cocotb Fork of cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  • nightly .github/workflows/benchmark.yml

Size: 6.97 MB - Last synced: 9 months ago - Pushed: 11 months ago

ishraqtashdid/cocotb Fork of cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  • c4e457b6596ee2872274c3b7d2615ad8ddacd70c .github/workflows/regression-tests.yml

Size: 6.48 MB - Last synced: 9 months ago - Pushed: about 2 years ago

oliverbm67/cocotb Fork of cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  • nightly .github/workflows/benchmark.yml

Size: 6.91 MB - Last synced: 8 months ago - Pushed: 9 months ago

marcinwoj/cocotb Fork of cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  • nightly .github/workflows/regression-tests.yml

Size: 5.57 MB - Last synced: 9 months ago - Pushed: over 3 years ago

ZPNMiaoHeng/neorv32-verilog Fork of stnolting/neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  • nightly .github/workflows/main.yml

Size: 1.77 MB - Last synced: 9 months ago - Pushed: 9 months ago

benrod3k/litex Fork of enjoy-digital/litex
Build your hardware, easily!
  • master .github/workflows/ci.yml

Size: 14.7 MB - Last synced: 8 months ago - Pushed: over 1 year ago

timothyscherer/cocotb Fork of cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  • nightly .github/workflows/benchmark.yml

Size: 7.03 MB - Last synced: 8 months ago - Pushed: 8 months ago

TinyRetroWarehouse/spi-fpga Fork of jakubcabal/spi-fpga
SPI master and SPI slave for FPGA written in VHDL
  • nightly .github/workflows/main.yml

Size: 2.78 MB - Last synced: 8 months ago - Pushed: about 3 years ago

bmWhale/neorv32 Fork of stnolting/neorv32
:desktop_computer: A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
  • nightly .github/workflows/riscv-arch-test.yml

Size: 171 MB - Last synced: 8 months ago - Pushed: over 2 years ago

npatsiatzis/uart
  • nightly .github/workflows/coverage.yml
  • nightly .github/workflows/coverage_16450.yml
  • nightly .github/workflows/coverage_pyuvm.yml
  • nightly .github/workflows/formal.yml
  • nightly .github/workflows/regression.yml
  • nightly .github/workflows/regression_16450.yml
  • nightly .github/workflows/regression_pyuvm.yml

Size: 12.7 MB - Last synced: 7 months ago - Pushed: 7 months ago

retar-kamuy/vunit Fork of VUnit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
  • master .github/workflows/push.yml

Size: 13.8 MB - Last synced: 6 months ago - Pushed: 6 months ago

cronomantic/neorv32-verilog Fork of stnolting/neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  • nightly .github/workflows/main.yml

Size: 176 KB - Last synced: 15 days ago - Pushed: 15 days ago

ktbarrett/cocotb Fork of cocotb/cocotb
Coroutine Co-simulation Test Bench
  • nightly .github/workflows/benchmark.yml

Size: 7.77 MB - Last synced: about 13 hours ago - Pushed: 1 day ago

gsomlo/litex Fork of enjoy-digital/litex
Build your hardware, easily!
  • master .github/workflows/ci.yml

Size: 16.1 MB - Last synced: 1 day ago - Pushed: 1 day ago

00mjk/fletcher Fork of abs-tudelft/fletcher
Fletcher: A framework to integrate FPGA accelerators with Apache Arrow
  • master .github/workflows/examples.yml
  • master .github/workflows/test.yml

Size: 7.71 MB - Last synced: 8 months ago - Pushed: over 2 years ago

wyvernSemi/OsvvmLibraries Fork of OSVVM/OsvvmLibraries
Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  • master .github/workflows/Test.yml

Size: 162 KB - Last synced: 2 months ago - Pushed: 2 months ago

00mjk/litex Fork of enjoy-digital/litex
Build your hardware, easily!
  • master .github/workflows/ci.yml

Size: 14.7 MB - Last synced: 8 months ago - Pushed: over 1 year ago

lianakoleva/litex Fork of enjoy-digital/litex
Build your hardware, easily!
  • master .github/workflows/ci.yml

Size: 15.2 MB - Last synced: 8 months ago - Pushed: 8 months ago

npatsiatzis/fizzbuzz
  • nightly .github/workflows/coverage.yml

Size: 10.8 MB - Last synced: 7 months ago - Pushed: 7 months ago