GitHub / abdelazeem201 / ASIC-Design-Roadmap
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/abdelazeem201%2FASIC-Design-Roadmap
Stars: 327
Forks: 42
Open issues: 0
License: mit
Language: Verilog
Size: 5.75 MB
Dependencies parsed at: Pending
Created at: about 4 years ago
Updated at: 5 days ago
Pushed at: 8 months ago
Last synced at: 2 days ago
Topics: awesome, awesome-list, fpga, hardware, verilog