Maharishi1313/little_proc

RISC-V RV32IM Core

Language: C++ - Size: 7.58 MB - Last synced at: about 7 hours ago - Pushed at: about 9 hours ago - Stars: 1 - Forks: 0

pkpkp456/Learn_System_Verilog

Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.

Language: Jupyter Notebook - Size: 17.2 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 0

MUDAL/Altera_FPGA_Projects

This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.

Language: C - Size: 206 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 9 - Forks: 0

Khallil973/RV32I-Core

RV32I 5-Stage Pipelined CPU

Language: Verilog - Size: 218 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

Nidhinchandran47/DV200

A go-to repository for exploring, learning, and mastering RTL design and verification.

Language: Verilog - Size: 895 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 3 - Forks: 0

OrsuVenkataKrishnaiah1235/RTL-Coding

"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"

Language: Verilog - Size: 8.66 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 6 - Forks: 3

meeeeet/UART-DesignAndVerification

Language: SystemVerilog - Size: 79.1 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

AhsanAliUet/Ahsan-Ali-Interests

My interests and some collaborations

Size: 2.93 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0