MUDAL/Altera_FPGA_Projects

This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.

Language: C - Size: 201 MB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 7 - Forks: 0

Khallil973/RV32I-Core

RV32I 5-Stage Pipelined CPU

Language: Verilog - Size: 218 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

Nidhinchandran47/DV200

A go-to repository for exploring, learning, and mastering RTL design and verification.

Language: Verilog - Size: 895 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 3 - Forks: 0

OrsuVenkataKrishnaiah1235/RTL-Coding

"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"

Language: Verilog - Size: 8.66 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 3

meeeeet/UART-DesignAndVerification

Language: SystemVerilog - Size: 79.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

AhsanAliUet/Ahsan-Ali-Interests

My interests and some collaborations

Size: 2.93 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0