samiyaalizaidi/Equalizer

Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications

Language: Verilog - Size: 536 KB - Last synced at: about 2 months ago - Pushed at: 4 months ago - Stars: 6 - Forks: 1

samiyaalizaidi/FIR-Filter

Implementation of a low-pass FIR filter in Verilog HDL.

Language: Verilog - Size: 249 KB - Last synced at: about 2 months ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 0

Sinashourjeh/QIAU-Bachelor-of-Computer-Enginnering Fork of Awrsha/QIAU-Bachelor-of-Computer-Enginnering

This repository contains projects developed by students of the Bachelor of Computer Engineering program at Qazvin Islamic Azad University (QIAU). The projects cover various topics in computer engineering, including digital systems, microprocessor, logical circuits, computer graphics, and etc..

Language: Perl - Size: 2.03 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

Amey-Thakur/DIGITAL-LOGIC-DESIGN-AND-ANALYSIS-AND-DIGITAL-SYSTEM-LAB

CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>

Size: 185 MB - Last synced at: 2 months ago - Pushed at: about 1 year ago - Stars: 10 - Forks: 1

Prabhas1273/decode-zero-one

Size: 0 Bytes - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

AhsanAliUet/Ahsan-Ali-Interests

My interests and some collaborations

Size: 2.93 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

alirezahabib/sut-dsdl

Digital Systems Design Lab, Sharif University of Technology Fall 2022

Language: Verilog - Size: 11.2 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

alirezahabib/sut-dsd

Digital Systems Design, Sharif University of Technology Fall 2022, Instructor: Dr. Amin Foshati

Language: Verilog - Size: 5.55 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

matscats/digital-processor

Seven instructions digital processor for general purpose.

Language: VHDL - Size: 361 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 2

Pedro-H-Braga/Disciplina-Sistemas-Digitais-2022.2

Circuitos para resolução das tarefas da matérias Sistemas Digitais do IFRN-CNAT do curso de Redes de Computadores

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melchisedech333/verilog-experiments

:space_invader: My studies with Verilog and notions of digital systems.

Language: Verilog - Size: 391 KB - Last synced at: 29 days ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

AryanAhadinia/DigitalSystemsDesignCodes

My Verilog Codes for Digital Systems Design Course

Language: Verilog - Size: 4.33 MB - Last synced at: 2 months ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

MohammadYAmmar/Design-Moore-FSM-project-via-Quartus-and-ModelSim

Simulate a statement through Moore FSM, With a full explanation. This project was my last additional course project for Verilog in Digital Systems Design during my BS in Computer Engineering

Language: Verilog - Size: 9.47 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

naman-0316/DSDS-EEE-Lab

DSDS (Digital system design and synthesis) Lab and class programs of 2021 - 25 batch.

Language: Verilog - Size: 35.2 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

PhilipSanM/Robotics_DigitalSystems_and_Cheese

Repository focused on giving a complete introductory course to digital systems, applied to robotics and automation.

Language: HTML - Size: 69.6 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0